1. Field of the Invention
This invention relates generally to integrated circuits and more particularly to yield enhancement circuits by implementing redundant sub-circuits for faulty sub-circuits of the integrated circuits. Even more particularly this invention relates to yield enhancement circuits for substituting redundant columns of memory cells for faulty columns of memory cells in memory arrays such as static random access memory (SRAM).
2. Description of Related Art
Yield enhancement circuitry for integrated circuits, particularly for memory integrated circuits, is well known in the art. Memory integrated circuits are formed of multiple arrays of memory cells. Each memory array is constructed of rows and columns of memory cells. Normally, the rows of memory cells are selected by an address decoder. The columns of memory cells are bounded by read/write buffers that retrieve data from and store data to the selected memory cell. A column decoder provides a selection mechanism to guide data from a selected column to the read/write buffers. The output of the read/write buffer is transferred to an input/output driver and receiver to transfer the data between the memory cells and external circuitry.
In the processing of the memory circuits, contamination or defects within the process will cause faults within the memory circuit. To compensate for the faults within the memory circuits, redundant rows and columns of memory cells are appended adjacent to the array or within the array of memory cells. In array organizations where multiple columns of memory cells are arranged to provide data for one input/output circuit, a redundant column may be placed adjacent to the columns and connected for implementation to only those columns associated with the input/output circuit. This organization places a large overhead in space for the redundancy. For instance if the input/output circuit has eight columns for containing the data and one column of redundancy, the overhead for the redundancy becomes approximately 12.5%.
As process techniques have improved, contamination and defects have decreased, thus ameliorating the need for such high levels of redundancy. Rather than having one redundant column of memory cells per input/output circuit, one redundant column is added, associated, or appended to an array of memory cells. In some cases, there may be one redundant column of memory cells for multiple arrays positioned on a substrate. The wiring to connect the redundant column of memory cells so that it can be connected within the array or arrays is relatively long and affects the performance of the memory.
Refer now to FIG. 1 for a description of a memory having a redundant column of memory cells associated with an input/output circuit. In this illustration the memory is constructed of two arrays of memory cells 5 and 10. Within the two memory arrays 5 and 10, sub-arrays 15a, 15b, . . . , 15z and 20a, . . . , 20z are composed of columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z. A redundant column 35 of memory cells 40a, 40b, . . . , 40z is positioned to be associated with the columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z. 
Each of the columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z is connected to one of the redundancy implementation switches 45a, . . . , 45z. The redundant column 35 of memory cells 40a, 40b, . . . , 40z is connected to all the redundancy implementation switches 45a, . . . , 45z. 
The redundancy implementation switches 45a, . . . , 45z are connected to the fuse box 50 which provides the necessary programming or indication of a fault within the columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z. If no fault occurs, the columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z are connected directly to the read/write buffer 55. However, if a fault is detected during testing of the memory, the fuse box 50 is programmed to indicate the column 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z containing the fault. The programming of the fuse box 55 sets the appropriate redundancy implementation switch 45a, . . . , 45z associated with the faulty column 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z such that the redundant column 35 of memory cells 40a, 40b, . . . , 40z is now connected to the read/write buffer 55.
The read/write buffer 55 contains the necessary circuitry to sense data from or store data in a selected memory cell within a selected column of the columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z. The column decoder 70 is connected to the read/write buffer 55 to select which of the columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z is to be activated for sensing or storing data. The column decoder 70 receives an address, which is decoded to provide the selection of the column 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z. The read/write buffer 55 is connected to an input/output circuit 60. The input/output circuit 60 contains a receiver to acquire data from the connector 65a, 65b, . . . , 65m, 65n, . . . , 65z and a driver to transfer data to the connector 65a, 65b, . . . , 65m, 65n, . . . , 65z. The connector 65a, 65b, . . . , 65m, 65n, . . . , 65z is in communication with external circuitry for transfer of the data.
It is apparent to one skilled in the art that the number of columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z associated with an input/output circuit 60 determines the efficiency of the redundancy of the array. This assumes that there is one redundant column 35 of memory cells 40a, 40b, . . . , 40z within each sub-array 15a, 15b, . . . , 15z and 20a, . . . , 20z. In embedded memory applications, especially for SRAM applications, there may actually be a one-to-one correspondence of columns 25a, . . . , 25z of memory cells 30a, 30b, . . . , 30z to the input/output circuits 60.
Referring now to FIG. 2 for a description of a memory having a redundant column of memory cells associated with multiple memory arrays. In this illustration the memory is constructed of two arrays of memory cells 105 and 110. Within the two memory arrays 105 and 110, sub-arrays 115a, 115b, . . . , 115z and 120a, . . . , 120z are composed of columns 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z. A redundant column 135 of memory cells 140a,140b, . . . , 140z is positioned to be associated with the memory arrays 5 and 10. Each of the columns 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z is connected to one the redundancy implementation switches 145a, . . . , 145z. The redundant column 135 of memory cells 140a, 140b, . . . , 140z is connected to all the redundancy implementation switches 145a, . . . , 145z. 
The redundancy implementation switches 145a, . . . , 145z are connected to the fuse box 150 which provides the necessary programming or indication of a fault within the columns 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z for all the sub-arrays 115a, 115b, . . . , 115z and 120a, . . . , 120z. If no fault occurs, the columns 125a, . . . , 125zof memory cells 130a, 130b, . . . , 130z are connected directly to the read/write buffer 155. However, if a fault is detected during testing of the memory, the fuse box 150 is programmed to indicate the column 125a. . . , 125z of memory cells 130a, 130b, . . . , 130z containing the fault. The programming of the fuse box 155 sets the redundancy implementation switch 145a, . . . , 145z associated with the faulty column 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z such that the redundant column 135 of memory cells 140a, 140b, . . . , 140z is now connected to the read/write buffer 155.
The read/write buffer 155 contains the necessary circuitry to sense data from or store data to a selected memory cell within a selected column of the columns 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z. The column decoder 170 is connected to the read/write buffer 155 to select which of the columns 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z is to be activated for sensing or storing of data. The column decoder 170 receives an address, which is decoded to provide the selection of the column 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z. The read/write buffer 155 is connected to an input/output circuit 160. The input/output circuit 160 contains a receiver to acquire data from the connector 165a, 165b, . . . , 165m, 165n, . . . , 165z and a driver to transfer data to the connector 165a, 165b, . . . , 165m, 165n, . . . , 165z. The connector 165a, 165b, . . . , 165m, 165n, . . . , 165z is in communication with external circuitry for transfer of the data.
It apparent to one skilled in the art that the number of columns 125a, . . . , 125z of memory cells 130a, 130b, . . . , 130z within the sub-arrays 115a, 115b, . . . , 115z and 120a, . . . , 120z and the total number of all the sub-arrays 115a, 115b, . . . , 115z and 120a, . . . , 120z determines the length of the connections to the redundant column 135 of memory cells 140a, 140b, . . . , 140z. The length of these connections has a detrimental impact on the performance of the memory when the redundant columns 135 of memory cells 140a, 140b, . . . , 140z are implemented.
U.S. Pat. No. 5,742,556 (Tavrow, et al.) describes a redundancy scheme for semiconductor RAMS. This integrated circuit memory structure includes a plurality of regular columns of memory cells arranged in a sequence such that each regular column except the last one has an associated adjacent regular column. Each regular column has associated sense amplifier circuitry and read write driver circuitry. The structure also includes a programmable element that responds to stimulus by providing a signal that identifies one of the regular columns as a defective column.
U.S. Pat. No. 5,612,918 (McClure) describes redundancy architecture that reduces the complexity of the redundancy structure because it has fewer pass gates in the redundant decoder.
U.S. Pat. No. 5,257,229 (McClure, et al.) describes a column redundancy architecture for a read/write memory whereby an integrated circuit memory has its primary memory array arranged into blocks with redundant columns. Each of the redundant column decoders includes a set of fuses for storing the column address responsive to its associated redundant column.
U.S. Pat. No. 5,134,584 (Boler, et al.) describes a configurable device that uses a plurality of parallel units that are made up of cells for storing individual bits of information. These cells are identified by address signals and selected to be interrogated. If a nonfunctional cell is detected within a parallel unit that parallel unit may be decoupled from the interrogator. The remainder of the parallel units is then shifted to different interrogators.
U.S. Pat. No. 4,807,191 (Flannagan) describes redundancy for block-architecture memory. This is explained as two stacks of memory blocks. Each block of sense amplifiers is coupled to a memory block. Located at the bottom of each stack of memory blocks is a redundant block of columns of memory cells. The redundant sense amplifier is also coupled to a redundant global data line. An input/output multiplexer is coupled to all of the global data lines. If one of the redundant columns replaces a defective column for a particular address, then the redundant global data line carries data which corresponds to the external data.
U.S. Pat. No. 4,691,301 (Anderson) describes a semiconductor memory with redundant column circuitry that includes a row of shared predecoder and predecoders. The selected decode output is determined by the row shared predecoder. A switch bank of single pole-double throw switches selects between a normal and a redundant output. When a defective column is replaced, all of the switches between the redundant column and the defective column have their states changed and the redundant column is activated. The address for each of the columns then has a lower position than the defective column incremented by one.